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IP.com Disclosure Number: IPCOM000014832D
Original Publication Date: 2000-Mar-01
Included in the Prior Art Database: 2003-Jun-20

Publishing Venue



Disclosed is a translation approach to reduce the number of instructions which need to be executed by a binary translation system. More specifically, the approach is designed to allow accurate 100% system level binary translation to make use of control flow and live range anal- ysis while preserving complete accuracy in the presence of unpredictable exceptions in full system binary translation. To maintain a consistent architectural state, emulation and binary translation systems must compute all observable data values computed by an input program, even if these values may never be accessed subsequently. For many architectures, this information includes condition code values which may be implicitly set by all or most instructions of an architecture. (Exam ples of such architectures are IBM System/390, DEC VAX and Intel x86). This incurs computation overhead to compute unused data values. In addition, due to system-specific nature of condition code setting, significant work may have to be expended to compute the condition codes accurately on another system. While liveness information can be used to identify unused condition code computation, this information is necessarily incomplete for full system simulation. More particularly, such liveness analysis cannot detect control flow which may occur due to exception or trap oper- ations, e.g., due to page faults.