Implementing the System Call Vectored Instruction in the Power 4 Microprocessor
Original Publication Date: 2000-Mar-01
Included in the Prior Art Database: 2003-Jun-20
Implementing the System Call Vectored Instruction in the Power 4 Microprocessor Disclosed is a mechanism for supporting the System Call Vectored instruction in the Power 4 superscalar, superpipelined, out-of-order gigahertz processor core. This instruction provides many challenges to an out-of-order processor, and these challenges were aggravated by the high frequency target of the design. This mechanism uses many existing mechanisms within the Power 4 core instruction control circuitry to satisfy the architectural requirements of the 'scv' PowerPC/AS instruction. This instruction is unique within the PowerPC/AS architecture; it has aspects that are similar to interrupts, and it has other aspects that are similar to branches. This instruction stores the return address in the Link Register, which is often used for subroutine calls. Interrupts, however, use the Save and Restore Register 0 (SRR0) for the same purpose. Likewise, this instruction uses the Count Register in place of SRR1 to save the Machine State Register (MSR). But, this instruction also acts very much like an interrupt in that it redirects the fetch address and alters the MSR.