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A Conflict-Free Multi-Output Port FIFO Memory Composed of Memory Elements Slower than the Total Line Rate

IP.com Disclosure Number: IPCOM000014884D
Original Publication Date: 2001-Apr-15
Included in the Prior Art Database: 2003-Jun-20

Publishing Venue

IBM

Abstract

A memory system is disclosed which has one write port and several read ports. It emulates a FIFO with the restriction that the read ports are not permitted to stop reading. Such a memory is useful in applications where packets destined for a particular output port (read-port) may arrive much more quickly than that output can read them. Therefore they must be stored temporarily. The particular feature of this memory system is that it consists of several memory elements, each of which is slower than the required data throughput of the system, but which are combined in such a way as to make a system with the required (much higher) aggregate throughput. The memory system comprises several memory elements, each of which is slower than the required data throughput of the system, but which are combined in such a way as to make a system with the required (much higher) aggregate throughput. Time is divided into slots of fixed duration. During each time slot a unit of data of fixed width (a cell) may arrive at the write (input) port. Each cell is accompanied by the number of the read (output) port to which it will be sent. During the same time slot, one of the output ports reads a cell from the data-store. The outputs are serviced in round-robin fashion.