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A DSP architecture for multi threaded applications

IP.com Disclosure Number: IPCOM000014886D
Original Publication Date: 2001-Feb-20
Included in the Prior Art Database: 2003-Jun-20

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The following propose a novel solution at the architectural and system level for multi channel real-time applications. Applications such as modem banks (like V.90), VoIP gateways (audio coders), wireless base station (Like GSM), and even switches can benefit from this architecture by providing a much better cost/performance ratio. The document outlines a novel architecture for a DSP (and even other purpose CPUs) that can allow the use of small and inexpensive DRAM in place of fast, large and expensive SRAM. The new architecture is especially suitable for multi unrelated threaded applications, nevertheless it can be utilized also for general tasks. The new DSP does not include a cache architecture and performs all the tasks in a deterministic manner. The new architecture can be applied to many existing cores with a small investment and almost no changes are required to existing legacy code. It may utilize the IBM embedded DRAM solution. The advantages of this architecture can provide IBM with the leading edge that is needed in order to play a significant role in the DSP market. Content · Introduction