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Automatic Method for Verifying NDR and Simulation Models Disclosure Number: IPCOM000014941D
Original Publication Date: 2001-Oct-20
Included in the Prior Art Database: 2003-Jun-20

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Automatic method for verifying NDR and simulation models ABSTRACT This paper describes the methods of checking New Delay Rule (NDR) and simulation models. NDR verification includes the generation of Standard Delay Format (SDF) file from NDR and checking the correctness of all entries in the file. Simulation model checking includes checking the functionality of Verilog and VITAL books, io path propagation delay back annotation and timing checks back annotation. PERL Practical Extraction and Report Language script is used to develop this method. This method is applied on library CMOS7SFLPGA which is developed in IBM YASU, Japan. Various bugs have been found in NDR and models. 1. Introduction