Method and Apparatus for Temporally Shared Access to a Common JTAG Interface
Original Publication Date: 2001-Sep-13
Included in the Prior Art Database: 2003-Jun-20
Disclosed is an invention which allows parallel independent JTAG (IEEE 1149.1) instruction streams to overlap using a single physical interface. Local interfaces include both JTAG (IEEE 1149.1) and IIC (Integrated Circuit Interconnect, Phillips Corp, public domain). The interfaces merge on chip in a common JTAG bus. This bus was not designed to accommodate temporally concurrent transfer streams. When such an overlap occurs, the transfer is garbled, leading to incorrect data exchange and/or incorrect future operation. Proper operation may be insured via a software semaphore "lock" which allows only one interface to be active at a time. This invention overcomes this limitation in most cases by allowing parallel independent instruction streams to interleave. Software overhead is reduced and interface performance enhanced. JTAG transfers do not have adequate provision allowing them to be temporally delayed. Furthermore, the instruction/data transfer sequence is "atomic" while in the Shift-IR or Shift-DR states. IIC transfers may be paced by the slave device following the acknowledge bit timing. This opens a window for buffering one of the on-chip JTAG data streams (native JTAG vs IIC translation) while in non-shift states (see Figure 1). Some of the other JTAG/TAP controller states create buffering problems as well (see Figure 2), dependant upon the active instruction in the IR (JTAG Instruction Register). The IIC-to-JTAG translated data stream is prevented from initiating while the native JTAG stream has the TAP controller in Shift-IR/DR or other "IIC Hold" state. Given the delay inherent in software (related to re-programming the native JTAG controller to perform primitive steps of a transfer), this period is used to release bursts of IIC-initiated activity to perform transfers. The current TAP/IR state is restored following the burst, leaving the native JTAG stream intact (see Figure 3). If the native JTAG data stream resumes transfer while the IIC translated JTAG activity is ongoing, the native stream (TCK/TMS) is buffered while the IIC stream completes. Following the TAP/IR restore sequence, this buffered stream is unbuffered at high-speed into the on-chip JTAG, "catching up" with the state now required by the native interface. This buffering can be limited to a predictable size when the data transfer size has a maximum limit. The JTAG buffering period may be extended to the start of the shift-DR state if the native IR saved indicates that the data transfer is uni-directional to the native JTAG receiver. If extending the invention further to general (full chip) scan rings is a requirement, the limited buffer size would still work, necessitating only that the IIC transfer halt when the buffer is "nearly full" (soon enough to restore state while continuing to buffer), and re-start from beginning following completion of the native JTAG request. This disclosure covers both implementations.