PLL Unlock Detector
Original Publication Date: 2002-Apr-11
Included in the Prior Art Database: 2003-Jun-20
Disclosed is a method to detect uniform locking condition of the PLL for any divisor values of the PLL dividers. This method generates unlock signal of the PLL with "up" output, "down" output of phase frequency detector, divided reference clock (Ref. Clock) and divided VCO Clock. An unlock detector (ULD) is proposed to implement this method. This ULS indicates the timing when PLL is locked to a target frequency and phase. This ULD detects the lock condition in a same accuracy independently of divisor values. Figure 1 shows the circuit of the PLL which uses the proposed ULD. 1 According to this method, "Unlock" signal of the PLL is generated by using "up" output, "down" output of a phase frequency detector, divided reference clock (Ref. Clock) and divided VCO clock.