Method for verification of system bring up code in simulation
Original Publication Date: 2002-Jan-06
Included in the Prior Art Database: 2003-Jun-20
Disclosed is a methodology for verification of system bring-up code in system simulation using a broadside load method for scan ring initialization. A model is built representative of the systems that will actually be brought up in the lab, then run the bring-up code against the simulator model before hardware is available in the lab. These models contain one or more of the processor, IO/bridge, and memory controller chips. A scan ring is a chain of latches accessed serially through the IEEE JTAG Test Access Port which are used for initialization and/or debug. One of the steps in the initial program load (IPL) process is to initialize certain configuration specific latches through these scan rings. This process requires doing a scan read of the target ring (read the value of each latch serially into memory through the JTAG interface), modify the specific configuration latch values, then scan the data back in through the JTAG interface. This procedure is repeated for each ring in each chip that requires initializing. In simulation (depending on the simulator used), this process can take days. By using the "broadside load" function, instead of initiating a long-scan, we can perform this scan operation without running any sim cycles thus significantly reducing the time needed to run the IPL. The simulator must provide a method to read and modify the value of latches and other signals by referencing them by name. Part of the simulation model build operation is to generate a file called a scandef. The scandef file contains the name of the scan ring, it's length (number of latches), address, name of each latch, position of the latch within the ring, and the initial value of the latch (inversion mask). The latch names in the scandef must match the sim model for the broadside load function to work.