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Congestion Driven Placement System Using Mid-Cut Partitioning Disclosure Number: IPCOM000015325D
Original Publication Date: 2002-Feb-03
Included in the Prior Art Database: 2003-Jun-20

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This invention describes a novel wiring congestion metric and proposes placement methods that use this metric in top-down physical design of v ery l arge s cale i ntegrated (VLSI) circuits so that routability is improved. Due to lack of a clearly defined congestion measure, previous approaches have addressed routability indirectly by focussing on minimizing cut size (in a partitioning based placement algorithm) and/or total wire length. Using proposed metric a new congestion driven the placement problem is formulated and efficient solutions for same are presented. Introduction: Many researchers have tried to loosely define a measure of congestion based on average wire densities and have shown that such a measure is directly related to wire length itself because the chip area is usually fixed. This concept of global congestion however is not meaningful as local hot spots will never be taken into account by such a measure. For example, a very high congestion in a small area and a low congestion everywhere else would still lead to a low average congestion. In this study we propose a new measure of congestion and propose partitioning based placement algorithms that can alleviate congestion. Wire Congestion: This disclosure overcomes the problem and illustrates the application of a new measure of routability based