Method for specifying short defect position of gate and common buslines after patterning second metal layer in TFT-LCDs
Original Publication Date: 2002-Aug-01
Included in the Prior Art Database: 2003-Jun-20
1 Figure 1 This article describes two methods for specifying position of short circuit between gate-line and common-line in AMLCDs with which common-lines and gate-lines are placed by turns in the same layer in parallel and which all common-lines are tied together in left and right edges with negligible low resistance. These methods enable to correct the defect at low cost. Figure 1 shows the short circuit in the AMLCDs. The gate-line resistance (terminal GL to GR) and common-line resistance (terminal CL to CR) are expressed as Rg and Rc in the following descriptions. The two methods are as follows.