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Soft Error Resistant Latch

IP.com Disclosure Number: IPCOM000015445D
Original Publication Date: 2001-Dec-01
Included in the Prior Art Database: 2003-Jun-20

Publishing Venue

IBM

Abstract

The soft error resistant latch is a modified version of an latch which uses the master-slave configuration, so there are really two latches that make up one latch. Also, the latches are basically cross-coupled inverters so both data input and the inverse of the data input are stored at the critical nodes of both latches. Transistors are placed in series with the branches to the VDD and ground rails to prevent the wrong path from conducting if there is a charge injected at a critical node that would normally cause a soft error. Node names and what they mean: L1_T The node of the first latch that has the same value as the data. L1_C The node of the first latch that has the inverse value of the data. L2_T The node of the second latch that has the same value as the data.