Ultra-shallow junction doping and simultaneous silicide contact formation by selective plating
Original Publication Date: 2002-Oct-03
Included in the Prior Art Database: 2003-Jun-20
This invention disclosure is based on the unique features of electroless plating that by depositing a very thin layer of electroless metal containing phosphorus or boron over the active area of a silicon surface, and later subject to a high temperature anneal will lead to the simultaneous formation of highly electrically conductive metal silicides and doping to form an CMOS FET device. The key innovations of this application are the selective deposition of nanometer thin films of metal alloys on the surface of the P and N gates and on the interspace surface between the STI and the P an N gates (see figures 11 to 16 below) . Further processing after alloy deposition is high temp. thermal annealing for the alloy to form silicides and to induce thermal doping to create the CMOS FET devices . To obtain the selective metallization it is necessary , first to apply a catalyst layer on the selected areas. This layer consists of nanoparticles of Pd , Ni, or Co .(Fig. 11 on the detailed process outline). The catalyst layer can be deposited by immersion the wafer in a colloidal solution of palladium such that the palladium particles are trapped in the microcavities of the porous silicon as shown in the detail process flow below, or by surface ion implantation or by sputtering thru a mask. It is essential that the catalyst is not buried deep and that stays mainly on the surface as a thin monolayer.(otherwise will not be active to the plating bath).- From this point of view, sputtering may be preferable to ion implant , unless the implant can be controlled to the surface substrate . Also, the particles should cover only the top surface of the P and N gates and not its lateral walls ,so a unidirectional or well collimated ion beam is required. Yet another alternative for seeding is to do amphorus silicon implant over the wafer. The amphorus silicon at the gate, source/drain area will trap the colloidal palladium when the wafer is immersed in a palladium colloid solution. Next the catalyzed selected areas are exposed sequentially and selectively to 2 different plating baths.- Using lithography , first P well is protected and electroless Ni , electroless CoP,electroless CoWP, or electroless NiPW are plated in the NFET region (Fig.13). Next, again using lithograpy the the N well region is protected and e'less NiB is plated on the P FET region (Fig 15). Further high temperature thermal anneal will complete the process.