Repair method for line open defect of LCD
Original Publication Date: 2002-Feb-15
Included in the Prior Art Database: 2003-Jun-20
Disclosed are the repair methods for open-circuit defect of wirings and short-circuit defect between the first (gate or storage capacitor lines) and second wirings (signal lines) in the thin film transistors (TFT) array substrate ,which has IPS (In Plane Switching mode)-HRP(High Resolution Process) structure, for use in a liquid crystal display (LCD) device. This structure has the character that common electrodes made of ITO (Indium-Tin Oxide) are located immediately above signal and gate lines. Therefore, in order to separate electrically the common electrodes and the repaired portions by means of the laser CVD method, the common electrodes are cut off completely by the laser beam. The cut sections have the depth not to cut off the gate and signal lines located immediately below the common electrode.
FIG.1 is a plan view showing the thin film transistors (TFT) array substrate of IPS- HRP type liquid crystal display (LCD) device in the display area. FIG. 2 shows a sectional shape at the position corresponding to a X-X’ line in FIG. 1. The glass substrate 1 is provided with TFT 2 having signal lines 3, gate lines 4, storage capacitor lines 5, common electrodes 6, pixel electrodes 7, an amorphous silicon layer and the like deposited thereon. The TFT 2 is a switching element for controlling a drive voltage to the pixel electrode 7, and is provided on an intersection portion of the signal line 3 and the gate line 4. Each signal line 3 is the one for transmitting a display signal to the TFT 2, arranged on the insulating layer 8A, and provided to be extended in a predetermined direction at each predetermined interval. Each gate line 4 is the one for transmitting a scanning signal to the TFT 2, arranged on the glass substrate 1, and provided so as to be extended in a direction approximately perpendicular to that where each signal line 3 continues at each predetermined interval. Each storage capacitor line 5 extended in parallel to the gate line 3 is provided and electrically connected to each common electrode 6 in the outer peripheral portion. Here, the storage capacitor line 5 is arranged so as to cross the central portion in the vertical direction of each pixel region 9 which is defined by being surrounded by two signal lines 3 adjacent to each other and two gate lines 4 adjacent to each other. The common electrodes 6 made of ITO (Indium-Tin Oxide) are provided on the insulating layer 8B, and are formed in an approximately lattice type so as to be located immediately above the respective signal lines 3 and the gate lines 4. It should be noted that the common electrodes 6 are set to have width wider than those of the signal line 3 and the gate line 4. Here, for the insulating layer 8B, the same material as that of transparent resist capable of securing a large film thickness (several micrometers) that is about ten times larger than a conventionally used nitride film or the like (film thickness: less than 1micrometer), for example, acrylic resin or the like is used. The pixel electrodes 7 made of ITO are electrically connected to the source electrodes 10 of the TFT 2 via the contact holes 11 formed in the insulating layer 8B.