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Low Power Flip-Flop Circuit Disclosure Number: IPCOM000015619D
Original Publication Date: 2002-Mar-18
Included in the Prior Art Database: 2003-Jun-20

Publishing Venue



·Disclosed is a Flip-flop circuit which can accomplish lower power dissipation than the conventional one. It consists of the clock generation part with an Exclusive-NOR and the latch part that has only a slave latch. This configuration results in operation with half of the expected frequency and along with a simple single latch, it can minimize physical size as well as power dissipation. · The key points of this circuit are in the clock generation part which enables the clock to be half for the normal operation and the latch part which does not have the master-slave type latch. (1) Clock generation part It consists of two inverters and an Exclusive-NOR. The configuration of the first inverter and an Exclusive-NOR generates very narrow pulses at both edges of the original clock. Then, the other Inverter after an Exclusive-NOR can generate the inverted phase of the signal with narrow pulses coming out of an Exclusive-NOR. These two signals with narrow pulses become actual clock signals (CLK1 and CLK2) for the latch. Fig.A shows the clock generation part in this Flip-flop circuit. (2) Latch part It consists of two clocked-inverters and an inverter within the feedback loop. Fig.B shows the schematic of the latch part. · The combination of these two parts can cut power dissipation of clock tree in half since the clock into latches become half of original clock frequency. Also, it can minimize physical size as the latch circuit itself is much simpler than the conventional master-slave latch. Fig.C shows the simulation results of this low power Flip-flop circuit. Low Power Flip-Flop circuit