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Prefetching considering Resource Constraint of the Architecture Disclosure Number: IPCOM000015630D
Original Publication Date: 2002-Feb-21
Included in the Prior Art Database: 2003-Jun-20

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A program is disclosed that generates prefetch instructions considering resource constraints of the target architecture. Prefetch instructions can hide latency of momory load operation. However, since an prefetch instruction also uses a load/store unit, we have to consider resource usage of the target architecture (the number of registers and utilization of functional units) to execute prefetch instructions efficiently. The program generates prefetch instructions in following procedure: In quadruple representation, prefetch instructions are inserted before every memory loads. In quadruple representation, dataflow optimization eliminates partially redundant prefetch instructions.