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CMOS Differential Signal Modulator and Variable Gain Amplifier

IP.com Disclosure Number: IPCOM000015648D
Original Publication Date: 2002-Aug-18
Included in the Prior Art Database: 2003-Jun-20

Publishing Venue

IBM

Abstract

CMOS DIFFERENTIAL SIGNAL MODULATOR AND VARIABLE GAIN AMPLIFIER Analog circuits utilizing merged division and multiplication functions offer flexibility in design of advanced integrated systems for performing various signal processing functions such as signal modulation, noise rejection and gain control. The realization of these microelectronic circuits in CMOS technology commonly employs a current pooling technique, such that differential signal division and multiplication are obtained while signal flows are balanced and reached in an equilibrium state. These circuit structures can be referenced to Ref. 1 and Ref. 2. In fact, the current pooling circuit requires a high gain amplification for high-bandwidth operations that is difficult to achieve with low voltage CMOS implementations. The high gain operation can result an increase of power consumption with poor voltage switching characteristics and often causes a stability problem. Fig. 1 presents a compact current-mode low-voltage CMOS modulator circuit for an improved design to provide high-bandwidth differential signal processing operations. The advantages of the circuit is low power consumption, good stability and excellent dynamic characteristics. The modulator (Fig. 1) contains two folded current squarer circuits with PFET devices of P1, P2 and P3, also P4, P5 and P6. The physical sizes of these PFET's are identical. The squaring function of the PFET circuits can be referenced to Ref. 3 and Ref. 4 for the unfolded NFET structures. The modulation signal is shown as an input current Iw in the diagram. The differential high frequency signal, Vin- and Vin+, is merged through the NFET pair of N1 and N2. The bias current Im is for establishing a current bias for the differential circuit structure mirrored (1:1) through transistors N7, N9 and N10. The current mirror produces the paired bias currents of Id9 and Id10 at the drains of N9 and N10. The drain currents of N1 and N2 are provided as Id1 Id9 Iin and Id2 Id10 Iin, where Iin is the differential signal current produced by the differential signal inputs of Vin- and Vin+, and Id9 Id10 Im. The output current of the first squarer, which is sum of the drain currents of P2