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System-Level Modeling and Performance Evaluation Methodology Disclosure Number: IPCOM000015676D
Original Publication Date: 2002-Mar-12
Included in the Prior Art Database: 2003-Jun-20

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Today's system-on-chip (SoC) design methodology is based on IP reuse. Systems are composed of preexisting building blocks which are taken from component libraries. Depending on the abstraction level of the component models, the functionality of the system can be specified on various levels of detail. Once a system model is composed on a specific abstraction level the overall functionality can be validated already in an early stage of design. While functional validation of systems is tightly connected to every phase of design, architectural performance evaluation is not integrated in the overall design flow. To evaluate a system architecture, additional performance models are necessary which are dedicated to solve a specific performance question. As a consequence more than one performance model per building block is necessary and reuse of these models in a future system design process is not possible in most cases. The proposed concept combines functional models with performance aspects and allows the integration of performance evaluation in the overall SoC-design flow. A system is a combination of several building blocks which are taken from a library of abstract models, one model per component. Every model is comprised of two layers, a functional and a data collection layer, as shown in Fig.1. Fig.1: 2-Layer Modeling Approach 1