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Regulated Delay Line with Look-Up Table

IP.com Disclosure Number: IPCOM000015689D
Original Publication Date: 2002-Apr-01
Included in the Prior Art Database: 2003-Jun-21

Publishing Venue

IBM

Abstract

Disclosed is an architecture of Regulated Delay Line to be composed on digital Integrated Circuit. This architecture provides application logic designers, especially designers using Gate Array, with an easy way to compose a Delay Line stabilized against variation of operating temperature, operating voltage, and manufacturing process. Delay Locked Loop (DLL) circuit is not used here, but an open loop control with a programmable Look Up Table achieves stability of propagation delay in Delay Line, which allows more flexibility than one using DLL. Pin pulse width Tpw Delay Measurement Circuit