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Interrupt Scheduler for processor with cache Disclosure Number: IPCOM000015696D
Original Publication Date: 2002-Apr-01
Included in the Prior Art Database: 2003-Jun-21

Publishing Venue



Disclosed is the method to reduce the overhead of the interrupt process with just interrupt controller changing. In traditional method, all of interrupt handling process are performed at the time when the interrupt occurred. But most of the interrupt handling process have not to respond to the interrupt immediately. In this disclosure method, each original interrupt source is latched at the interrupt controller, then the latched interrupt is provided to the delay logic. Each delay logic has each programmable delay timing. The ORed signal of each delay logic output is provided to the processor. The processor performs to the interrupt handling process of all of the interrupt latched in the interrupt controller. This method can eliminate the number of suspend and resume process by the interrupt. The following figure 1 and 2 indicates the timing chart and the block diagram. Figure 1