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PCI-X Hold Time Compensation Mechanism Disclosure Number: IPCOM000015797D
Original Publication Date: 2002-May-27
Included in the Prior Art Database: 2003-Jun-21

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One of the difficulties in designing any PCI device is managing the capture of control and data input signals from a PCI bus that has 0 ns input hold time, while also meeting an output hold time of 2 ns when driving those same signals. The problem is further compounded for PCI-X devices which must meet both PCI and PCI-X timing requirements using the same physical I/O pads and typically much common circuitry. Solutions which rely on clock tree (clock distribution network) latency to meet the PCI output hold time have extreme difficulty capturing input signals within the signal valid time window. Using a separate input signal capture clock can help, but the hold time problem is then moved to internal paths which traverse the two clock domains. Often the solution is to add delay to input or internal signal paths to create a later signal valid window. Adding delay circuitry to the many affected signal paths is costly and fraught with difficulties when the design is implemented on a VLSI chip which must be tolerant of wide variances in device delays due to potential variances in the fabrication process. The PCI/PCI-X Hold Time Compensation Mechanism inserts a polarity hold latch into the input signal path using an early version of a PCI clock. The latch is transparent during the beginning of the input signal valid window, but captures the signal prior to the end of the signal valid window, thereby extending the hold time of the signal. This solution allows for the internal clock cycle to be delayed relative to the PCI bus while minimizing the delay or “padding” circuitry that is generally associated with PCI designs. Using a delayed internal cycle eases the task of meeting output signal hold time requirements and provides more setup time for long control paths that must include unregistered input signals from the PCI bus. The delay introduced by the transparent latch is unacceptable for PCI-X timing requirements however, so a multiplexer is provided to select a conventionally registered version of the input signal during PCI-X mode operation. The difficulty of meeting both PCI-X 133 MHz and PCI 66 MHz timing requirements in the same device is recognized by the PCI-X addendum. PCI-X devices are required to be PCI compliant, but are only required to meet the PCI 33 MHz timing standard. Use of the PCI/PCI-X Hold Time Compensation Mechanism allows designers to successfully meet both the PCI-X 133 MHz and PCI 66 MHz timing requirements in the same device, without the time consuming and expensive process of adding and tuning delay circuitry. This is particularly important for designers of high performance PCI/PCI-X I/O adapters which must operate in both PCI and PCI-X server systems. The PCI performance of such adapters would be unacceptable at only 33 MHz. The input valid timing windows for PCI and PCI-X modes of operation are shown in Figure 1. A combined PCI/PCI-X device must have input capture circuitry capable of functioning with either of these windows depending on the present mode of operation.