Driver circuit suitable for variable capacitance loads
Original Publication Date: 2002-Jun-01
Included in the Prior Art Database: 2003-Jun-21
Disclosed is a driver circuit suitable for variable capacitance loads. In general a higher slew rate makes a bigger margin of setup/hold time, but causes serious overshooting and bounce noise for some data patterns, so it finally reduces setup/hold time. The transfer rates are 33, 66, 100 and 133MB/s in Ultra DMA mode. The slew rate of an ATA bus driver is selected to match the transfer mode, using a kind of flat cable.