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An Enable Signal Circuit for Multiple Small Banks

IP.com Disclosure Number: IPCOM000015887D
Original Publication Date: 2002-Jun-01
Included in the Prior Art Database: 2003-Jun-21

Publishing Venue

IBM

Abstract

Title of Disclosure : An Enable Signal Circuit for Multiple Small Banks Inventor : Toshio Sunaga, Shinpei Watanabe, Kohji Hosokawa For DRAM chips that consist of many small-sized banks, this disclosure provides an area-efficient circuit method to activate those small banks. The previous invention proposed a virtual bank method as an effective way to achieve high data rates for random row accesses (1). In this architecture, the chip consists of many small array blocks, where a self-timed circuit in each block controls the whole timing chain including row address latch, sense amplifier activation, write-back, and precharge, thus those blocks work as if there were many banks. It realizes multiple bank access operations without complex bank control schemes found in conventional DRAMs. When conventional methods to activate those many banks are exploited, many bank enable signal lines become necessary to wire all over the chip, and this causes a significant impact on chip size. Fig. 1 shows three examples of those conventional schemes. In the DRAM chip, there are four large blocks, and each block is sectioned further into 256 banks (32 in horizontally and e ight in vertically). Thus, the chip has 1,024 small banks. In actual implementation, a segmented row decoder with M1 main word lines and 4-8 polycide word lines per each main word line is assumed. To operate those banks independently, there is a control circuit at the corner surrounded by a sense amplifier block and the segmented row decoder in each bank. For each bank, it is necessary to provide a bank enable signal, and it requires some circuits and wiring areas. 1