Browse Prior Art Database

High speed access by RAM-buffered bus cycles for hardware accelerators

IP.com Disclosure Number: IPCOM000015908D
Original Publication Date: 2002-Jun-26
Included in the Prior Art Database: 2003-Jun-21

Publishing Venue

IBM

Abstract

Abstract This publication describes an advanced method accessing embedded busses in simulation models running on hardware accelerators as well as on workstations. An advanced “instrumentation-logic” and the matching method is introduced, which accesses the stimuli-data out of a preloaded RAM. This publication will be used for IML-code-verification (initial micro program) during virtual poweron. Virtual poweron is the process to verify the IML code before the real hardware prototype is available. The “Virtual-hardware” consists of a simulation model loaded into a hardware accelerator box and a program connecting the service-element to the hardware accelerator as shown in figure 1. 1.Introduction The subject of IML testing is to access registers by means of the (embedded) localbus and to read/write scanrings of the simulation model. This can be done by: 1. Accessing the scanrings of any chip in the model using the simulator API. This is called a broadside load.