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Testing: WLR Padsharing Disclosure Number: IPCOM000016010D
Original Publication Date: 2002-Nov-16
Included in the Prior Art Database: 2003-Jun-21

Publishing Venue



Title: Wafer Level Reliability: Optimization of devices in the scribe line by implementing a novel padsharing technique William R. Tonti Toshiharu Saitoh IBM MicroElectronics, Essex Junction VT 05452 1. Introduction: With each new generation of semiconductor devices, chip and die size are proportionally decreased so that corresponding chips per wafer are substantially increased. This results in severe space limitations for test structures required necessary to monitor process and device parameters. This is particularly true for (but not limited to) production phases where test structures (process and parameter control monitors) can only be placed within the dicing channel, or the scribe line used to singulate associated chips. Typically the test structures are small with respect to the associated chip and scribe line area, and can be placed between or underneath probing pads. Under this criterion the limiting factor becomes the that are physically possible to place within the scribe line. Decreasing scribe line area implies a decreasing pad availability and hence a decrease in the number of associated test structures.