Browse Prior Art Database

Hub to Hub Bus

IP.com Disclosure Number: IPCOM000016045D
Original Publication Date: 2002-Jul-12
Included in the Prior Art Database: 2003-Jun-21

Publishing Venue

IBM

Abstract

1 Introduction 1.1 Overview The following described System is defined as a multi node machine. Each node consists of several Processor Chips, Cache Chips, Memory Controller Chips and IO-Chips. In addition, a single Hub Chip is assigned to each node. The Hub to Hub (HtH) bus is used to establish communication between Hub Chips in a multi-node environment. Each node consist of several processors connected to one Hub Chip. In general the HtH bus has two different usages. First, the HtH bus is used to distribute nodal information which is required System wide and therefore on all Hub Chips. Second, the HtH bus provides an access path from every processor in the System to every engine defined on a Hub Chip. Engines on a Hub Chip are defined as nodal Run-Control and Serviceability Engines to control processor chips on a node. High Level Diagram Hub Chip x Hub Chip y