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Method for Modeling Negative Hold Timing Specifications Disclosure Number: IPCOM000016054D
Original Publication Date: 2002-Dec-28
Included in the Prior Art Database: 2003-Jun-21

Publishing Venue



Disclosed is a method for modeling negative hold timing specifications in an event simulation environment. In the effort to extract ever increasing hardware performance for a given chip technology, very tight tolerances are specified with respect to latch setup and hold times. Latch setup time is defined as the time the data signal must be stable before the arrival of the clock to the latch. Latch hold time is defined to be the time the data at the latch must remain stable after the arrival of the clock to the latch. The performance of today's logic gates introduce the concept of a "negative hold" timing specification. A negative hold timing specification defines the time before the arrival of the clock to the latch, where the data must remain stable. This definition allows data, intended for the next clock cycle, to change prior to arrival of the latch clock for the present clock cycle. The specification of negative hold timing constraints introduces problems when checking for hold time violations during event simulation with back annotated SDF (Standard Delay File) timing data. Timing checks are derived from the clock event at the latch (clock rise or clock fall) relative to data change events at the same latch. For setup time checks, the time the data change event occurred is recorded, then the time of the subsequent clock event is subtracted from the data change time. If the resulting time period is less than the setup time specification, a setup time violation is detected. For hold time checks, the time the clock event occurred is recorded, then the time the data changed is subtracted from the clock event time. If this time period is less than the hold time specification, a hold time violation is detected. The hold time check is based on the assumption that the hold time requirement is after the arrival of the clock to the latch (min hold point of Fig. 1a). Therefore it is difficult to model negative hold time checks with the current checking algorithm. Data change events, which are actually valid, will appear as erroneous setup timing errors with current timing check implementations (in the valid range depicted in Fig. 1b). The VITAL (VHDL Initiative Towards ASIC Libraries) standard defines a method for modeling negative timing constraints for simulation, which require additional SDF timing generics, simulation support, timing rules, and hardware modeling. This disclosure defines a method to achieve the desired timing checks, in simulation, with a much simpler modeling change. The change is to modify the setup time check to each latch with a negative hold time specification. For these types of latches, a timing violation is detected only if the data event time, relative to the latch clock, is less than the setup time specification and greater than the absolute value of the hold time specification. This check assures that setup timing violations are properly restricted to the invalid setup range depicted in Fig. 1b, and false timing violations are not detected for data changes that occur in the valid range depicted in Fig. 1b. A flowchart of the revised setup time checks, with negative hold support, is illustrated in Fig. 2. There is no hold time check defined after the latch clock event for a negative hold time specification, so the setup time check encapsulates both setup and negative hold time checks. Positive hold time checks are performed as usual, after the reference clock edge. 1