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Efficient method to simulate multiple clock domains in a cycle-simulation model

IP.com Disclosure Number: IPCOM000016074D
Original Publication Date: 2002-Dec-12
Included in the Prior Art Database: 2003-Jun-21
Document File: 3 page(s) / 84K

Publishing Venue



Disclosed is a method to model multiple clock domains in a cycle based simulation model. By providing an efficient scheme to simultaneously drive all clock domains, minimal over-sampling of the simulation model will occur. With minimal over-sampling of the simulation model, a more efficient overall simulation performance will be realized.

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Efficient method to simulate multiple clock domains in a cycle-simulation model

   In a cycle simulation model of a compiled logic design, gate evaluation is rank-ordered across all cones of logic in the design.

That is, when the simulation cycle is executed, all logic gates in the design are re-evaluated even though the inputs may not have changed state. (This contrasts with an event based simulator, where a logic gate will only be evaluated when one of its inputs changes state.) By nature of a cycle simulation environment, no logic gates in a domain of logic will be updated (i.e., change value) if the clock(s) which feed that domain are inactive. If a design contains multiple clock domains (i.e., multiple asynchronous clocks feeding separate cones of logic), then a simulation execution will, effectively, evaluate some logic whose clocks are active and some logic whose clocks are inactive. This execution of logic gates which have no active clock is termed "over-sampling." Over-sampling uses simulation execution time (and thus, computer resource) without updating any logic. The method disclosed herein minimizes over-sampling in a cycle based simulation model. This reduction in simulation execution reduces compute time and increases overall simulation cycles achieved in a given period of time.

The main idea is to add clocking 'intelligence' to the simulation model. This intelligence is the ability to predict the next rising edge of a clock by logically ORing the clock domains together. When the clocks are stable (i.e., no rising clocks) no model execution is performed. The intelligent simulation clock will maintain a master clock which advances directly to the rising edge of the next earliest clock. The master clock represents the logical simulation time which is shared with the user's run-time environment. With this clocking scheme, the user's run-time environment will see the simulation model evaluated only at rising-edge clock times. Because the model is not executing unnecessary simulation cycles during 'dead' clock times, the simulation model advances more efficiently.


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Figure 1 : frequency relationship between 3 clock domains

In the Figure 1 example, if the simulation model contains clock domains with frequencies at 27Mhz, 50Mhz, and 100Mhz, the user environment will see time advance from 0 to 10 ns (100Mhz domain) to 20ns (50Mhz and 100Mhz domains) to 30 ns (100 Mhz domain) to 37 ns (27Hhz domain) to 40 ns (50Mhz and 100Mhz domains) and so on. Assuming that logic storage elements are only updated on rising clock edges, then this...