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A METHOD FOR SPEEDING-UP PROCESSOR BY USING PIPELINE REROUTING

IP.com Disclosure Number: IPCOM000016087D
Original Publication Date: 2002-Oct-19
Included in the Prior Art Database: 2003-Jun-21

Publishing Venue

IBM

Abstract

Problem Modern superscalar microprocessors use multiple-execution pipelines. In many cases, some of these pipelines are identical. For example, a processor may have two pipelines for execution of floating-point instruction. During the execution of an instruction, it may be forced to stay in a specific pipeline stage for a long period of time (more than a single cycle). This can delay the instructions that follow the initial instructions in the pipeline, since they cannot proceed to an occupied stage. Delays in the pipeline decrease the rate in which instructions are handled by the processor, and thus increases the execution time of programs. In many cases, instructions are stalled in a pipeline, even though the resources that are needed for their execution are available in another (identical) pipeline. In today’s microprocessors, an instruction remains in the same pipeline it started in and waits for the pipeline stages to become available, even if similar stages in an equivalent pipeline are free. Solution