Browse Prior Art Database

Automatic Embedded Array Disclosure Number: IPCOM000016102D
Original Publication Date: 2002-Oct-18
Included in the Prior Art Database: 2003-Jun-21

Publishing Venue



A process is disclosed for automatic compression and extraction of embedded SRAM cell geometries from semiconductor chip layout data. The compression algorithm is based on the reduction of contiguous groups of array cells into larger blocks. Physical location information is collected for the larger blocks, allowing the location of any individual array cell to be accurately calculated. Current microprocessors contain large embedded SRAM memories along with functional logic. It is often necessary to locate the exact physical placement of any given array cell in these memories. An obvious solution would be extraction of physical coordinates for every cell, but the subsequent data volume becomes impractical. To combat this, the compression algorithm unions all array cells which share physical borders into a single large block. The X and Y coordinate for the lower left corner of the large blocks (from chip origin) is then read out into a text file along with delta X and delta Y values, orientation of the bounded cells, and a cell type identifier. In the header of the file, the size of each array cell is given for each valid cell type identifier. Using this information, it is possible to calculate a micron offset, from chip origin, for any given cell in the array.