Browse Prior Art Database

Improved Trench Capacitor with Low-Resistance Fill Disclosure Number: IPCOM000016140D
Original Publication Date: 2002-Aug-21
Included in the Prior Art Database: 2003-Jun-21

Publishing Venue



The disclosure describes a structure for a deep-trench storage capacitor with a low series resistance fill inside the trench electrode. The trench series resistance will be about 10X lower than that of doped polysilicon. Also the disclosure describes a method for the formation of a conductive material into a high aspect ratio aperture in a substrate. The procedure is to despite a highly conformal metal oxide followed by a conversion process to convert metal oxide to a conductive layer. And ,it shows a structure for a deep trench storage capacitor in a vertical transistor DRAM with a metallic material inside the trench electrode which is separated from any region of the single crystal substrate with a method for the selective formation of a low-resistance material (salicide) by thermal anneal of a metal oxide in proximity to a silicon thin film. In view of a composite silicon substrate plate), thin node dielectric such as silicon nitride, thin LPCVD silicon (poly) and conformal metal oxide is shown in Diagram A. The same film stack after thermal anneal is shown in Diagram B. The conformal metal oxide has been converted to a metal silicide, and portion of the thin LPCVD silicon has been consumed by the silicide formation. A portion of the LPCVD silicon remains in proximity to the thin node dielectric. A cross section view is shown in Figure 1. A substrate, such as silicon, contains a trench pattern formed in pad film such as LPCVD silicon nitride. The trench pattern is formed by means of photolithogrpahy and dry etch such as reactive ion etching (RIE). In figure 2 a collar region has been formed in the upper region of the trench, and a buried plate outdiffusion has been formed into the lower region of the trench. A thin node dielectric has been formed by conventional means such as thermal nitridation, LPCVD SIN deposition, and re-oxidation. Figure 3 shows a thin conformal LPCVD silicon layer deposited to a thickness less than 20% of the diameter of the trench pattern. Figure 4 shows a conformal metal oxide film such as AlOx, HfOx, ZrOx deposited by means such as atomic layer deposition (ALD) as described in this disclosure. In figure 5 the LPCVD silicon layer and metal oxide have been recessed in trench pattern by conventional means such as resist fill and recess and wet and dry etch of the metal oxide and LPCVD polysilicon fill. In figure 6 the structure has been subjected to a thermal anneal which causes the metal oxide to react with the LPCVD silicon to form a conductive silicide. The structure may optionally be capped (not shown) prior to anneal. Figure 7 shows the inventive structure which has been filled with LPCVD silicon and recessed using conventional means such as dry etch. The DRAM may subsequently be formed by conventional means. Figures 8&9 show the cross section views. An LPCVD silicon layer has been deposited and planarized prior to the thermal anneal which forms the metal silicide. Figure 9 shows the structure after thermal anneal and the formation of silicide. A third proposal is shown in Figure 10-13. In Figure 10 the LPCVD polysilicon fill has been recessed preferably by a photoresist fill, recess and etch of the exposed polysilicon. In Figure 11 the conformal metal oxide has been deposited. In Figure 12 the metal oxide has been converted to silicide 110 in regions where it is in contact with the LPCVD silicon fill . In Figure 13 an LPCVD polysilicon has been deposited and recessed and the structure is ready for subsequent formation of DRAM by conventional techniques. 1 Diagram A Diagram B