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Method and apparatus for scheduling dynamic trace groups to reduce peak power dissipation Disclosure Number: IPCOM000016149D
Original Publication Date: 2002-Sep-23
Included in the Prior Art Database: 2003-Jun-21

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A dynamic compilation program is disclosed being specially adapted to schedule instructions to reduce peak power dissipation. According to this invention, a program is compiled dynamically from a first representation (e.g., a first instruction set architecture, or other means for representing a program such as a virtual machine code or byte code) to a second representation (e.g., an unchanged, modified, extended or subsetted first instruction set architecture, or a different second instruction set architecture) while ensuring the generated code does not exceed a defined peak power limit. In one embodiment, the peak power is defined statically, e.g., during the program design cycle, or at boot time, in another embodiment, the peak power is defined dynamically in response to measurement taken during system operation. In one exemplary embodiment, the dynamic compilation program creates a target program consisting of tree regions, which have a single entry (root of the tree) and one or more exits (terminal nodes of the tree). The dynamic translation algorithm interprets code when a fragment of source representation (i.e., the instruction set or byte code in its original representation) code is executed for the first time. As base representation primitives (e.g., instructions or byte codes) are interpreted, the instructions are also converted to execution primitives for the target instruction set. These execution primitives are then scheduled into target code fragments which are saved in a memory. Any untaken branches, i.e., branches off the currently interpreted and translated trace, are translated into calls to the binary translator. Interpretation and translation stops when a stopping condition has been detected. A target code fragment of an instruction group is ended by a branch to the next target code fragment. According to the present invention, the scheduling step is optimized to derive the power dissipation which the program will trigger during each execution cycle, and it is determined whether scheduling an instruction in a specific slot will cause the power budget to be exceeded. If this is the case, the schedule is adapted such that by scheduling the instruction, the pwoer limit will not be exceeded in any given cycle. In one implementation of the present invention, this occurs by scheduling an instruction which would exceed the power budget in a later cycle where sufficient power dissipation budget is still available. Other optimization schemes which optimize both performance and power dissipation while remaining under said peak power limit can also be used in conjucntion with the present invention.