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A Method to Enhance Reliability of Integrated Circuits By Introducing Electromagnetic Radiation At Pre-Fuse Test to Facilitate Defect Discover So That Redundancy May Be Invoked Disclosure Number: IPCOM000016179D
Original Publication Date: 2002-Oct-18
Included in the Prior Art Database: 2003-Jun-21

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Defects occurring in the silicon level of integrated circuits are difficult to detect during test , especially those that are not electrically active at the time of test (potential reliability fails). One method of enhanced defect detection is to use a high test temperature to aid in defect-induced leakage currents. This invention would use this elevated temperature test technique but introduce in addition to the temperature, electromagnetic radiation to enable a defect lying at or below the silicon surface to become electrically active and, thus become easily detectable. Once detected, redundancy may be invoked to replace the defective element with a non-defective one. One potential application which may be useful to the reduction of one memory related failure mechanism known as the "Variable Retention Time" or VRT fail follows. It should be noted that this invention not only pertains to this mechanism/technique, but may be applied to other defects/techniques as well (light, radio waves, etc.). The root cause of VRT fails are Silicon defects such as stacking faults and dislocations that, for various reasons become electrically active as a function of time (non time zero detectable). In all integrated circuits, ion implants or diffusions of other than host species are used to locally change conductive properties of the host Silicon or Ge lattice. This induces localized stresses and strains in the host lattice and, as a means to relieve them, dislocations and stacking faults result. Steps may be taken to reduce the occurrence of these artifacts (anneals, etc), but no way is apparent in which they can be totally eliminated. The more dense the Silicon utilization by diffusions/circuitry, the greater the incidence of these faults and, the greater the likelihood that one may lie in a critical are of a cell that may give rise to unwanted electrical activity that we term "VRT". Detection of potential VRT fails in today's environment, requires high temperature/ long term tests to detect and eliminate (usually performed during module burn-in due to the increased time or the test rather than module or wafer final test). Fails occurring at burn-in are non-recoverable and detract directly from the yield. This invention teaches to first study VRT performance under the influence of electromagnetic radiation in the form of light at the wafer/chip level (wafer final test). It is assumed that the "light" (causing hole-electron pairs in the substrate) will enhance or encourage those cells on the chip with a propensity to exhibit VRT behavior to do so in a short period of time such that they may be detected and redundancy invoked so that they may be eliminated during wafer final test, thus improving the yield and reliability of the final product. Different frequencies of electromagnetic radiation may be applied so that different depths in the silicon may be stimulated (eg.: IR light could probe deeper than shorter wavelength light which would be usefull to excite surface defects. 1