SELF TIMED FLASH ADC ARCHITECTURE
Original Publication Date: 2002-Nov-29
Included in the Prior Art Database: 2003-Jun-21
Invention The invention permits the construction of very high speed (GHz), low power CMOS ADC, with improved metastability behavior due to the use of the arbiter circuit, reduced clock power dissipation, and easier clock routing due to the use of self-timed circuits. The treatment of metastability errors by using an arbiter type circuit instead of relying on metastable hardened latches is new. The comparators that form the flash converter are built to provide a completion pulse indicating that a decision has been achieved. A ratioed wide OR circuit generates a pulse that indicates that most of the neighbor comparators have reached a decision (majority signal). The arbiter passes the logic value of the comparator if it arrives in time (before the majority signal), and passes a zero if the comparator has not reached decision by the time the majority signal arrives.