Browse Prior Art Database

Method for Reduced Inductance Contacting for Semi-Conductor Test

IP.com Disclosure Number: IPCOM000016306D
Original Publication Date: 2002-Oct-18
Included in the Prior Art Database: 2003-Jun-21

Publishing Venue

IBM

Abstract

Disclosed in this publication is a method for Reduced Inductance Contacting for Semi-Conductor Electrical Test operations. In the semi-conductor test environment, higher than desired levels of inductance using existing contacting solutions are a problem. The inductance of the contactor modifies the inherent inductance of the environment that the device under test (dut) sees. Depending on device sensitivities and matching networks around the device, this change of inductance will at a minimum drive necessity for component re-tuning of the dut board. In severe cases, the dut will not function properly (causing the dut to oscillate) due to the additional inductance that the contactor is adding. Designing a contactor strategy that utilizes parallel conducting paths to reduce the inductance of the conducting path is the basis of this publication. Presently, there are no known contacting solutions that utilize parallel conducting paths for signal connections during semi-conductor electrical testing. The advantage of using a parallel contacting strategy is realized in reduced inductance influences due to the contactor. This lowered or reduced inductance is a key objective throughout the semi-conductor test industry. In fact, suppliers for contactors and/or contact leads promote their products based on lower inductance. A supplier with products of lower inductance values vs. that of their competitors, typically has bragging rights and as a result, market share. There are many ways to apply a parallel contacting strategy. One method may be to improve the application of existing products. Pogo pins as an example , may be taken to a level of electrical performance beyond the original intent or specification by the manufacturer. One pogo pin, providing a signal path between a device under test (dut) and a printed circuit board (pcb), has a measurable value of inductance. 2 pogo pins providing the same signal path, only now a parallel path, have less or reduced inductance value. In this example, improved performance is credited to the strategy of how the pogo contact is applied, not the mechanical design or electrical characteristics of the pogo pin itself.