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Resource Usage Analysis Method for Statically-scheduled Non-interlocked Pipelined Processors Disclosure Number: IPCOM000016357D
Original Publication Date: 2002-Nov-20
Included in the Prior Art Database: 2003-Jun-21

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Abstract A method is described which can be beneficial when used for debuging and visualizing instructions that use multiple resources on a single instruction issue or multiple issue pipelined processor. The method in particular may be used for developing tools to analyze hardware resource utilization of instructions to improve power/performance characteristics of programs, and for checking compiler produced programs for resource contention errors or utilization weaknesses. Background A number of hardware resources are required for executing a program on a processor. Each instruction in the program however uses only a subset of the hardware resources available on-chip. The number and type of resources used by an instruction may also change during the lifetime of an instruction in the processor, which usually spans from the time it is fetched from the memory to the time the processor finishes carrying out the all the operations specified by the instruction. In order to maximize the throughput of the processor, often more than one instructions are initiated (or issued) either in the same cycle (instruction-level parallel processing) or prior to the completion of instructions issued in the previous cycles (pipeline processing), provided it can be guaranteed that none of the instructions during their lifetime in the processor try to concurrently use resources used by a different instruction. In an interlocked processor, hardware circuits are used for providing such guarantees required for pa rallel or pipelined execution of one or more instructions. In a non-interlocked processor, it is the responsibility of the programmer or the compiler/tool that generates machine instructions to provide such guarantees using static instruction scheduling techniques.