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High Heat-Flux "Burn-in" Tool Disclosure Number: IPCOM000016393D
Original Publication Date: 2002-Dec-11
Included in the Prior Art Database: 2003-Jun-21

Publishing Venue



Many modern microelectronic and avionic systems have total dissipated power levels that are increasing with every new packaging design. Increases in power levels and densities combined with the market expectation of reduced package sizes lead to heat challenges that, if left unchecked or uncontrolled, can significantly shorten the operating life of the microelectronic components. Although this "increased power – decreased size" scenario has been prevalent for many decades, the industry's ability to make smaller microelectronic components mandates reduced dimensions for cooling components (e.g., coldplates and heat-sinks). Liquid cooling, typically a water and glycol mixture, overcomes most of the heat removal and transport limitations of air-cooled systems. Smaller heat sink volumes, elimination of audible noise, the ability to move rejected heat away easily from the user area, and significantly, increased system and chip reliability are all liquid-cooling characteristics. The problem is that only a few applications currently accept liquid-cooled electronics. The concept of a liquid-cooled PC and high-end mainframe or server has yet to gain general market acceptance. However, forecasted power levels of 360 Watts or higher have been made for future processors and modules during burn-in operation, therefore, the use of liquid-cooled techniques is most definitely needed. Therefore, any cooling technique should provide the following attributes so that chips approaching the above stated power level can effectively meet chip temperatures during burn-in: o A temperature rise of 100C between the chip and cooling fluid, High performance cooling with camber for multi-chip module conformability, A membrane interface for each module CP that will enhance thermal interface conductance, A continue feed of virgin thermal interface material so that peak performance is always achieved at the chip to coldplate interface,