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Generic Bus Debug and Test I/O Adapter Disclosure Number: IPCOM000016399D
Original Publication Date: 2002-Nov-01
Included in the Prior Art Database: 2003-Jun-21

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Today's hardware complexity requires a more aggressive approach to debugging tools. Due to some hardware failure mechanisms it is possible for a system to become unavailable and/or require rebooting during normal operation or test. This unavailability may be a result of a hung processor or bus, which will not allow the system to continue processing. When this type of conditions occurs, it is practically impossible to obtain traces of the system functions before the system becomes unavailable. As the system becomes unavailable so do all the facilities that are used to collect trace data. The ability to collect data can be maintained by using the Generic Bus Debug and Test I/O Adapter described further in this publication. The advantage of using this adapter is the ability to preserve extensive system postmortem trace information even under the worst conditions, including total power loss. This would include the sequence of instructions leading to the unfortunate system state, accessibility to the trace information independent of the system state, and user controlled trace information. The adapter would also have the ability to collect traces from a working system and test/debug the I/O bus . Adapter specific features: Specific Application Bus: PCI/PCI-X, universal adapter, infiniband, PCI-express, RIO, etc. Specific industry standard bus implementation. Microcontroller type device operating independently of the application bus. Decentralized computing Remote control/data transfer operation controlled by separate machine connected via communications port (serial, TCP/IP, etc.). External I/O for reporting Battery backup to allow operation after system power has failed. Data preservation module Nonvolatile storage for processor instructions and trace information.