Browse Prior Art Database

ASIC Dual Port SRAM with Redundancy Disclosure Number: IPCOM000016411D
Original Publication Date: 2003-Feb-28
Included in the Prior Art Database: 2003-Jun-21
Document File: 1 page(s) / 39K

Publishing Venue



For yield purposes, a dual port SRAM with redundancy is desired in an ASIC technology. From an existing 4-port SRAM design with wordline redundancy, the desired dual port SRAM is derived. Although the existing 4-port SRAM could be used as a dual port, the disclosed dual port SRAM allows for higher performance applications, while maintaining the same self-test controller.

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ASIC Dual Port SRAM with Redundancy

We have previously designed a 4-port SRAM that has wordline redundancy. This redundancy facilitates higher manufacturing yields by allowing redundant wordlines to replace wordlines that prove to be defective during manufacturing test. This 4-port SRAM uses a dual-port array cell with time division multiplexing (TDM) to achieve a 4-port function. That is, two operations per cycle are multiplexed to use a dual port cell in a 4-port function. Two ports are processed in the first operation of the cycle, and the other two ports are processed in the second operation of the cycle. This technique yields an area improvement compared to using a 4-port array cell without TDM. Compared to non-TDM designs, however, the associated cycle time must be longer to allow for both operations to be completed within the cycle.

It is possible to use this existing 4-port design for dual port applications by simply not using two of the four ports. However, the cycle time for the dual port application would still reflect that of the 4-port design (TDM), which is undesirable for some dual-port applications. A dual-port solution that yields a faster cycle time is preferred (non-TDM).

The disclosed design achieves the preferred faster cycle time by using an existing self-test mode control to alter the 4-port SRAM's internal clock timing for dual-port applications. This mode control, called Test M1, is used to switch between self-test mode and normal functional mode. In the disclosed design we also use Test M1 to control the internal TDM timing pulses that process the second operation of the cycle. In a dual-port application, this second operation is not needed, since only the two ports associated with the first operation of the cycle are used. In normal func...