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ASIC Dual Port SRAM with Redundancy Disclosure Number: IPCOM000016411D
Original Publication Date: 2003-Feb-28
Included in the Prior Art Database: 2003-Jun-21

Publishing Venue



For yield purposes, a dual port SRAM with redundancy is desired in an ASIC technology. From an existing 4-port SRAM design with wordline redundancy, the desired dual port SRAM is derived. Although the existing 4-port SRAM could be used as a dual port, the disclosed dual port SRAM allows for higher performance applications, while maintaining the same self-test controller.