Browse Prior Art Database

Enhanced Flash Memory Reporting Mechanism

IP.com Disclosure Number: IPCOM000016626D
Original Publication Date: 2003-Jul-07
Included in the Prior Art Database: 2003-Jul-07

Publishing Venue

IBM

Abstract

Today Flash memory technology is becoming more dense. Some servers even store the entire operating system and diagnostics on a series of Flash modules. In the past Flash modules held data that was more or less immune to data integrity problems. With the denser flash memories and with the smaller cell sizes, the incidence of single bit errors increases. This increase is then multiplied by the number of Flash modules in a system. When the system boots and there is a single bit error, the system must keep running by applying an Error Correcting Code (ECC) to the data. However, I/O pins are limited on the module and there is a requirement to ensure the same footprint is used for different size families of Flash modules e.g., 32 Megabit, 64 Megabit, 128 Megabit etc. It is not practical to use an I/O pin as an indication of an ECC error. The following circuit and command sequence allow the user to interrogate internal registers to determine if an ECC error occurred, the address or addresses that had the ECC error, and the number of ECC errors during this operating system load.