SPQL Enhancement for ASIC SRAM
Original Publication Date: 2003-Jul-09
Included in the Prior Art Database: 2003-Jul-09
ASIC SRAMs are tested at several voltage and temperature conditions, prior to being shipped to the customer. Passing SRAMs could be near a point of failure; however, due to marginalities within the SRAM's internal self-timing circuitry, such SRAMs could then fail in the customer's application. Disclosed is a design that allows for known margins to be asserted during test, thereby improving the shipped product quality level (SPQL).