Browse Prior Art Database

SPQL Enhancement for ASIC SRAM Disclosure Number: IPCOM000016692D
Original Publication Date: 2003-Jul-09
Included in the Prior Art Database: 2003-Jul-09
Document File: 2 page(s) / 48K

Publishing Venue



ASIC SRAMs are tested at several voltage and temperature conditions, prior to being shipped to the customer. Passing SRAMs could be near a point of failure; however, due to marginalities within the SRAM's internal self-timing circuitry, such SRAMs could then fail in the customer's application. Disclosed is a design that allows for known margins to be asserted during test, thereby improving the shipped product quality level (SPQL).

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SPQL Enhancement for ASIC SRAM

  The disclosed design allows the SRAM to be tested with more aggressive internal timings than those used within the normal functional mode of operation. As such, marginal SRAMs that could otherwise fail in the customer's application are more likely to fail at the tester and be discarded rather than shipped. Specifically, the disclosed design addresses write margin and read stability SPQL.

    Refer to the circuit schematic below. This circuit includes a delay chain of CMOS inverters, and the resultant delay is used to establish the pulse width of the SRAM's selected wordline. Note that the delay chain is tapped at three different nodes. These three nodes drive into the A, B, and C inputs of a selector circuit. For normal operation (WRITEMARG and READSTAB both 0), path A is selected - this is the middle of the three tapped nodes.

    During write testing, WRITEMARG is set to 1, and path B is selected. Path B is the earliest of the three tapped nodes, so this yields a reduced wordline pulse width. This reduces the write timing margin. Hence, an SRAM that tests good will have additional write timing margin in normal operation, when the wordline pulse width is larger (by two inverter stages).

    During read testing, READSTAB is set to 1, and path C is selected. Path C is the latest of the three tapped nodes, so this yields a widened wordline pulse width. This increases the time during which the memory cells are exposed to read stability fails (erro...