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Method for a noise rejection circuit that incorporates logic blanking and timed hysteresis control to eliminate false triggering due to noisy input signals

IP.com Disclosure Number: IPCOM000016694D
Publication Date: 2003-Jul-09

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a noise rejection circuit that incorporates logic blanking and timed hysteresis control to eliminate false triggering due to noisy input signals. Benefits include improved performance.