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In-Situ Resistane Probe for MTJ Stack Deposition

IP.com Disclosure Number: IPCOM000016713D
Original Publication Date: 2003-Jul-10
Included in the Prior Art Database: 2003-Jul-10
Document File: 3 page(s) / 66K

Publishing Venue



Resistance probe for in-situ calibration of thicknesses of thin layers used for fabrication of magnetic tunnel junction devices

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In-Situ Resistane Probe for MTJ Stack Deposition

  The tunnel junction stacks used for fabrication of magnetic random access memory (MRAM) devices consist of multiple layers of materials, with the thickness of some layers being less than 1 nm. For deposition of stacks with reproducible electrical and magnetic characteristics, it is thus very important to accurately calibrate the deposition rates for the individual stack layers. The present method for rate calibration involves depositing individual thick films of the individual materials and from which one calculates the time required to deposit the thickness required for the material in the stack. Since the rates can drift with time due to changes in process conditions or target usage, it is necessary to frequently calibrate them, which is time consuming. Moreover, the calculated rates using this method may not be very accurate, particularly for small thicknesses. In this disclosure we propose the use of an in situ resistance probe scheme using an oxidized silicon wafer with pre-fabricated contact pads for thickness calibration. This simple method can provide rapid feedback and can potentially be much more accurate than the presently used thickness calibration method. Additionally, the probe can be used to monitor and develop an optimized oxidation process for the tunnel barrier. By using multiple probes, it should be possible to use the current in-plane tunneling test method for in situ determination of the resistance and magnetoresistance (MR) of the complete stack.

    Figure 1 shows a schematic top and side view drawing of a 200 mm wafer with four-probe electrical contact lines that can be used for in situ probing of the resistance during deposition of the stack layers. For fabrication of the test wafer, an oxidized silicon wafer is patterned, etched and filled with Cu and polished to form the four contact fingers. A dual damascene process can be used for the formation of the Cu lines. In the next processing step, most of the length of the patterned probe fingers is photolithographically patterned and covered with a thick layer of SiO2 (> 1 m). Only a small region near the center where the deposition occurs and the probe contact regions near the edge of the wafer are left exposed. This ensures that the resistance is measured from near the center of the wafer with minimal interference from the probe fingers, and there is no shorting of the lines in other areas. The region near the contact probe would normally see no deposition because of the shadowing from probe pins and t...