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A High-Speed, Sum Addressed Content-Addressable Translation Cache. Disclosure Number: IPCOM000016766D
Original Publication Date: 2003-Jul-14
Included in the Prior Art Database: 2003-Jul-14

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Recent microprocessor address memory using a base, offset scheme is associated with a "load" or "store" (or any similar instruction) are usually two fields (called operands) which represent a pair of registers -- a base register, and an offset register. These registers are added together in order to create what is commonly known as an effective address(EA). The EA is then further translated through the use of an SLB, TLB, hash look-up, etc. to generate a real address(RA). The RA is then used to address memory (L2,L3,system memory, etc.). The process of generating an RA from an EA is know as translation. Since translation is a costly operation (> 10 cycles), microprocessors usually include a translation cache (or table), know as Effective to Real Address Translation Cache (ERAT) . Once the EA is known, it can be quickly looked up in the ERAT. In practice, though, computing an EA from the two operands is costly as well, since a high-speed adder is required to compute the EA. There is also the need to use the ERAT in special ways. For instance there are some instructions which require bits, other than EA, to be compared within the ERAT as well. They might be valid bits, cache protection bits, thread information bits, etc. They would be treated as special miscellaneous bits. In some cases the ERAT may be used to partially clear entries which are no longer required to be valid in the table. Since computing the sum of the two operands that generate an EA is difficult, an ERAT which implements a method for quickly adding-comparing is needed. The ERAT must also have a way of partially comparing bits, as well as "classically" (no special sum method; just simply the bits) comparing, and a way to make entries in the table invalid.