Concept for automatically selective clocking of synchronous circuitry
Original Publication Date: 1999-Oct-01
Included in the Prior Art Database: 2003-Jul-22
Today’s semicustom design flows require circuits to consist of large single-clocked state machines. Circuit concepts that derive internal clock signals from internal data can’t be handled by most design compilers and are hard to test with modern test methodologies. However, the downside of today’s design style is that clocking large amounts of flipflops at the same clock speed regardless of whether they are told to receive new data via the the individual “write enable“ inputs leads to excessive void power consumption.