Browse Prior Art Database

Scheduler with reordering for ATM Adaptation Layer 2 switches Disclosure Number: IPCOM000017126D
Original Publication Date: 1999-Oct-01
Included in the Prior Art Database: 2003-Jul-22

Publishing Venue


Related People

Alan Forbes Christian Huber [+details]


The AAL2 Switching ASIC ACE contains several AAL2 output queues. To determine, from which queue the next output ATM cell shall be built and sent from, a scheduler is implemented. The scheduler makes this decision based on the two parameters timeout and size. A queue should be scheduled, if either the timeout of the 1 st packet in the queue has occurred, or if the size of the queue exceeds 47 bytes. The scheduler is shown in figure 3. It is implemented as a calendar function where outgoing queues are marked. Time represented by the now pointer constantly increases and if it points to a filled calendar position, then the control block orders the transmission of a cell for that queue marked in the calendar. The implementation of the calendar is achieved using a RAM, covering an address range of 0 to 4095. Each address represents a timeslot of 2.7 us (representing one ATM cell at STM1 rate), resulting in a maximum timeout of approximately 11 ms (2.7us*4096). If the actual time, i.e. the now-pointer, points to address 4095, the next address will be 0.