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Optimized Overlay Measurement Algorithmen (based on existing signal detection software)

IP.com Disclosure Number: IPCOM000017673D
Original Publication Date: 2001-Jul-01
Included in the Prior Art Database: 2003-Jul-23

Publishing Venue


Related People

Sebastian Schmidt Rolf Heine Dietmar Ganz [+details]


At the production of memory and logic chips in the field of semi-conductor technology different structured layer must get fine aligned to other below. Currently is one layer in both dimension (X and Y) aligned to the layer below to which it should best fit related to the design manual (Figure 1). An optimized alignment is assuming a measurement of the misregistration in best quality. These measurements are performed at special test structures. The idea for new chip generations is to fit the actual printed layer to one layer in X and another in Y direction due to the very tough tolerances. Because both layers use different overlay test structures which generate different signals it is necessary to use different algorithmen for signal detection (contrast, slice level, resolution, reference signal) to obtain the best result (Figure 2).