Reducing skew between different clocks of a module during scan
Original Publication Date: 2001-Jul-01
Included in the Prior Art Database: 2003-Jul-23
Clock Skew between multiple clock domains in a module: A SOC design has many hierarchical modules with each module having independent clocks. These days most chips have multiple clock domains and hence any module could have clock speeds from very fast to very slow clocks. In scan mode of operation typically the same clock would be used, which means that all these multiple clock domains would run at the same clock frequency. After the layout of the module, it would be noticed that the skew between these different clock domains in the scan mode is a lot. This means, that a lot of capture violations during scan mode of operation and hence a lot of instability of the test pattern would occur. The consequence would be a loss of fault coverage. Problems with Layout tool: When there are different clock input pins to a module, the layout tools are not able to take care of the relationship with different clocks. After layout, a clock tree synthesis is performed by the layout tool to balance the load on the clock nets and hence control the skew between different clocks. Hence the clock tree synthesis takes care of the individual clocks only and the skew between different clocks has to be controlled manually. A loss of some accuracy follows and there is no clean data flow during the scan mode of operation.