Browse Prior Art Database

Central Interrupt System for Dual-or Multi-Core Dies such as S-Gold or M-Gold

IP.com Disclosure Number: IPCOM000017954D
Original Publication Date: 2001-Oct-01
Included in the Prior Art Database: 2003-Jul-23

Publishing Venue

Siemens

Related People

Authors:
Gerhard Forster [+details]

Abstract

The technical problem refers to a central interrupt handling for all cores and co-processors (for S-Gold e.g. PCP2). Until now, for every core and every co- processor one interrupt unit was used. The new solu- tion consists of using one flexible interrupt unit in- stead of one interrupt unit for every single core / co- processor. The following description informs the reader about the functional and principal of the idea (as outlined in the figure below):