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Partial Inner Loop Instruction Repeat Buffer

IP.com Disclosure Number: IPCOM000018220D
Original Publication Date: 2003-Jul-23
Included in the Prior Art Database: 2003-Jul-23

Publishing Venue

Motorola

Related People

Authors:
Larry Richard Tate James W. Stroming

Abstract

A.The Problem - Instruction fetch power is a significant component of overall power consumption in general purpose DSPs. In many real world DSP applications, 20% of the instructions consume 80% of the available machine cycles. The other 80% of the instructions consume the remaining 20% of machine cycles. Many of the most processing intensive algorithms will be implemented as highly optimized code inside loops. The innermost loops instructions execute with much higher frequency than the outer loop instructions. Most of the instruction fetch power consumption from inner loops. The problem is to reduce overall fetch power. Fetch power must be reduced while maintaining full programmability and not inconveniencing the programmer.