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Method for performing a critical path test of a fast digital circuit on slow test equipment

IP.com Disclosure Number: IPCOM000018571D
Original Publication Date: 2003-Aug-25
Included in the Prior Art Database: 2003-Aug-25

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Abstract

The critical path of a digital circuit (e.g. integrated circuit) is the longest path between sequential storage elements like e.g. flip-flops or latches. The timing of this critical path has to be checked during production test. The problem with this test is the low speed of the test equipment. It is difficult to check fast digital circuits with slower test equipment. Usually the signal transitions along the critical path do consume almost one complete clock cycle. If the chip tester is not able to supply a clock cycle, which is shorter than the delay of the critical path, the timing of this path can not be checked. If for example a chip tester of 100MHz must check a digital circuit of 200MHz, the chip tester is not able to stimulate and verify the critical path. Up to now the problem has been solved by using a local clock generator (PLL, phase locked loop), which supplies a clock to the circuit during the test process. For tests running at full circuit speed it is necessary to use a fast PLL with a clock cycle which is shorter than the cycle of the chip tester. The disadvantage is that thus the test runs asynchronously compared to the chip tester. In this case the tester can not stimulate any pins or perform checks on a cycle by cycle base. It just can search for a simple pass/fail indicator signal which is generated by the circuit itself (self checking tests). That way it is almost impossible to catch the first occurring timing violation. This would require parallel monitoring of several thousand flip-flops at each cycle and generating pass/fail depending on their contents. It is very likely to miss timing violations.